1. Field of the Invention
The present invention generally relates to a method of manufacturing semiconductor elements, and more particularly to a method of fabricating semiconductor elements having a multiwiring-layer structure (multi-level interconnection structure) in which a metal-filled low-resistance via-hole is formed in an interlayer dielectrics (insulating film).
2. Description of the Related Art
A conventional method for fabricating semiconductor elements is disclosed in, for example, Japanese Patent Kokai (Laid-open Publication) No. 11-260823. 
FIG. 6 of the accompanying drawings illustrates a cross sectional view of a semiconductor element which is fabricated by such a conventional method.
In FIG. 6, reference numeral 1 designates a Si substrate, reference numeral 2 designates an insulating film (thin layer), reference numeral 3 designates a first wiring layer, reference numeral 4 designates an interlayer dielectrics (insulating film) reference numeral 5 designates a via-hole, reference numeral 6 designates an adhesive layer, reference numeral 7 designates a W plug, and reference numeral 8 designates a second wiring layer.
As understood from FIG. 6, the insulating layer 2, the first wiring layer 3, and the interlayer dielectrics 4 are formed on the Si substrate 1 in this order. The interlayer dielectrics 4 has the via-hole 5 which is formed by a photolithographic process and an etching process. The wall of the via-hole 5 is covered with the adhesive layer 6, and the W plug 7 is formed in the via-hole 5. After the via-hole 5 is filled with the W plug 7, the second wiring layer 8 is formed.
A process for forming the W plug 7 has two major steps. One step is a W nucleus (seed) forming step and the other step is a W main portion forming step (i.e., W fill-in step).
FIG. 7 of the accompanying drawings illustrates a flowchart of a process for forming the W plug with supplied gases.
The first step is a nucleation step for forming a W nucleus for the W plug 7 (sub-steps S1 and S2). In this step, layers are formed by using WF6, SiH4, and H2, which are the main raw materials.
Specifically, in the first step, a wafer (Si substrate) is placed in a chamber (a device for forming the W plug) and is then heated to a temperature which is suitable for the W plug formation. Subsequently, a raw material gas SiH4 is fed to the chamber to form a Si layer on an adhesive layer, and then another raw material gas WF6 is additionally fed to the_chamber to form a thin W film on the Si layer. This thin W film is called a W nucleus or seed. The WF6 gas and the SiH4 gas_form the thin W film on the Si layer. It should be noted that the combination of the Si layer and the thin W film may be referred to as a “W nucleus.”
The second step is a step for forming a main W portion (sub-step S3). In this step, the supply of the SiH4 gas is stopped, and the W plug 7 is formed by using WF6 and H2 as the main raw materials.
In this procedure, after W films are formed in and over the via-hole 5 by a CVD (chemical vapor deposition) process, the surface is etched back to have only the W plug 7 remain in the via-hole 5.
When the via-hole 5 is provided on the first wiring layer 3, undesired substances 9, such as TiOx, which result in high resistance, often remain on the first wiring layer 3. If these substances 9 remain in the via-hole 5 (or between the adhesive layer 6 and the W plug 7), the resulting semiconductor element (or the via-hole) has a high resistance.